~13d ago

Staff Logic Design Engineer

United StatesUnited States·Us - Milpitaslead
EngineeringDesign Engineer
1 views0 saves0 applied

Quick Summary

Requirements Summary

PCIe, CXL, NVMe, USB, SAS, SATA Experience with Monitoring and/or Test & Measurement tools Experience with PCIe protocol (Gen4/Gen5/Gen6) and familiarity with TLP/DLLP/PHY layer concepts.

Technical Tools
EngineeringDesign Engineer

Teledyne Technologies Incorporated provides enabling technologies for industrial growth markets that require advanced technology and high reliability. These markets include aerospace and defense, factory automation, air and water quality environmental monitoring, electronics design and development, oceanographic research, deepwater oil and gas exploration and production, medical imaging and pharmaceutical research.​

We are looking for individuals who thrive on making an impact and want the excitement of being on a team that wins.

  

  

Teledyne LeCroy is a global leader in protocol analysis and test solutions for high-speed serial data communications. Our high-speed protocol analyzers are trusted by top-tier semiconductor and system companies to validate and debug cutting-edge technologies in data centers, AI/ML, storage, and networking.

We are looking for a top-notch Staff Logic Design engineer who has the right composition of knowledge, experience, team play, spirit and drive, to join a dynamic team that develops leading edge test and measurement products. Join our high-speed Protocol Team as a Staff Logic Design Engineer, where you'll architect and implement high-performance digital logic for protocol capture, analysis, and emulation. You’ll work on FPGA-based systems that decode and analyze High speed protocols (PCIe, USB, Ethernet etc.) in real time, collaborating with cross-functional teams to deliver industry-leading solutions.

Responsibilities

~1 min read
  • →RTL Design & Microarchitecture
    • →Develop synthesizable RTL (Verilog/SystemVerilog) for high-speed protocol, packet parsing, timestamping, and buffer management.
    • →Design high-throughput data paths and control logic optimized for latency, bandwidth, and resource efficiency.
  • →FPGA Development
    • →Target high-end FPGAs (Xilinx Versal, Intel Agilex); perform synthesis, P&R, timing closure, and resource optimization.
    • →Integrate PCIe IP cores, DMA engines, and custom protocol decoders.
  • →Verification & Debug
    • →Build SystemVerilog/UVM testbenches for block and system-level verification.
    • →Conduct simulation, waveform analysis, and functional coverage to ensure robust design.
  • →System Integration
    • →Collaborate with hardware, firmware, and software teams to bring up and validate protocol analyzer platforms.
    • →Support lab debug using logic analyzers, oscilloscopes, and in-system FPGA tools (ILA/SignalTap).
  • →Documentation & Process
    • →Create design specifications, interface documents, and verification plans.
    • →Participate in design/code reviews and contribute to continuous improvement of design practices.

Requirements

~1 min read
  • BS in EE, CS or Computer Engineering required
  • MS in EE is a plus
  • 7+ years of experience in digital logic design for FPGA or ASIC.
  • Strong proficiency in Verilog/SystemVerilog RTL design.
  • Experience with one or more of the following protocols: PCIe, CXL, NVMe, USB, SAS, SATA 
  • Experience with Monitoring and/or Test & Measurement tools
  • Experience with PCIe protocol (Gen4/Gen5/Gen6) and familiarity with TLP/DLLP/PHY layer concepts.
  • Hands-on with FPGA toolchains (Vivado, Quartus, etc.) and timing closure.
  • Knowledge of UVM, assertions, and simulation/debug tools (e.g., ModelSim, Vivado Simulator).
  • Solid understanding of CDC, clock domain design, and reset strategies.
  • Experience with protocol analyzers, packet capture, and timestamping logic.
  • Familiarity with AXI interconnects, memory controllers, and high-speed buffering.
  • Exposure to SERDES, PCIe IP integration, and link training/debug.
  • Scripting experience (Python, Tcl) for automation and test infrastructure.
  • Experience with hardware/software co-design, register maps, and embedded firmware interaction.
  • Prior work in test & measurement or semiconductor validation environments.
  • Location: Milpitas, CA
  • Travel: Minimal (<10%) for lab collaboration or customer support
  • Team Culture: Collaborative, fast-paced, and innovation-driven

  

$141,900.00-$189,200.000

The anticipated salary range listed for this role is only an estimate. Actual compensation for successful candidates is carefully determined based on several factors including, but not limited to, location, education/training, work experience, key skills, and type of position.

Teledyne and all of our employees are committed to conducting business with the highest ethical standards. We require all employees to comply with all applicable laws, regulations, rules and regulatory orders. Our reputation for honesty, integrity and high ethics is as important to us as our reputation for making innovative sensing solutions.

Teledyne is an Equal Opportunity/Affirmative Action Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability or veteran status, age, or any other characteristic or non-merit based factor made unlawful by federal, state, or local laws. ​

Location & Eligibility

Where is the job
Us - Milpitas, United States
On-site at the office
Who can apply
US

About this job

Who can apply
United States
Posted
13 days ago
Employer
has 887 open jobs on Jobera in 3 countries.

Listing Details

First seen
October 1, 2026
Last seen
October 15, 2026

Posting Health

Days active
13
Repost count
0
Trust Level
24%
Scored at
October 15, 2026

Signal breakdown

freshnesssource trustcontent trustemployer trust
Newsletter

Stay ahead of the market

Get the latest job openings, salary trends, and hiring insights delivered to your inbox every week.

A
B
C
D
Join 12,000+ marketers

No spam. Unsubscribe at any time.

Staff Logic Design Engineer