Quick Summary
Job Description SummaryThe Lead FPGA Firmware Engineer will be working to define requirements,
Roles and Responsibilities
o Analysing system requirements and defining functions to be implemented in Hardware.
o Strong Knowledge and experience of Model Based Design (MAT LAB Simulink, HDL coder, Xilinx System Generator)
o FPGA Firmware development.
o Analogue and digital Hardware design.
o Maintain legacy products including updates and improvements to extend product life span.
o Contribution to creating and maintaining manufacturing data packs.
o Writing functional specifications for design.
o Writing test specifications (Routine test, Type test, Test Harness).
o Participating in and contributing to design reviews.
o Ensuring designs are documented to Company standards.
Required Qualifications
o Degree or Higher in Electrical / Electronic engineering or equivalent experience with 8+ years experience
o Minimum 5+ years' experience of FPGA design using VHDL or Verilog.
o Strong all-round knowledge and understanding of electronic components & principles.
o Exceptional hardware / FPGA debugging skills.
o Experience with Altera, Microsemi, Xilinx FPGA devices and design tools (Quartus II, Libero SoC).
o Dynamic and proactive with ability to work on own or as part of a multi-disciplinary engineering team to resolve technical issues.
o Experience of designing hardware for real time control applications.
o High-speed digital hardware design and PCB layout skills.
Desired Qualifications
o Good verbal and written communication skills.
o Motivated great teammate, self-starter, results oriented.
o Agile development practices e.g., Scrum
o Scripting experience using Perl, Python
o Experience of version control, e.g., SVN, GIT
o Bug tracking tools, e.g., JIRA
o Power Electronics control system design.
o Knowledge of HVDC
Relocation Assistance Provided: Yes
Location & Eligibility
Listing Details
- First seen
- October 3, 2026
- Last seen
- October 3, 2026
Posting Health
- Days active
- 0
- Repost count
- 0
- Trust Level
- 56%
- Scored at
- October 3, 2026
Signal breakdown
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