Quick Summary
• High-speed TX and RX circuits• Serializer/Deserializer (SerDes) building blocks• PLLs, DLLs, CDRs, and clocking circuits• Equalization and signal conditioning circuits• Bandgap references,
Bachelor's or master's degree in electrical engineering, Electronics Engineering, VLSI, Microelectronics, or a related discipline.
Intel is looking for an experienced Analog Designer to join the IO Design Team in Bengaluru. In this role, you will be responsible for leading the design and development of advanced analog and mixed-signal circuits that enable high-speed chip-to-chip, package-to-package, and system-level connectivity for Intel's next-generation products.
The ideal candidate will have a strong background in transistor-level circuit design, high-speed IO architectures, and silicon debug. This position requires technical leadership, cross-functional collaboration, and ownership of critical IP blocks from concept through silicon validation.
Key Responsibilities-
• Lead the design, analysis, and optimization of analog and mixed-signal circuits for high-speed IO interfaces.
• Develop and drive architecture and circuit implementation for:
• High-speed TX and RX circuits
• Serializer/Deserializer (SerDes) building blocks
• PLLs, DLLs, CDRs, and clocking circuits
• Equalization and signal conditioning circuits
• Bandgap references, bias generation, and LDOs
• ESD protection and IO pad circuitry
• Perform detailed transistor-level design, simulation, and verification across multiple PVT corners.
• Drive design closure for performance metrics including bandwidth, jitter, noise, power, area, yield, and reliability.
• Collaborate closely with physical design teams on layout reviews and post-lay out optimization.
• Support silicon bring-up, characterization, root-cause analysis, and correlation between simulation and silicon measurements.
• Work with architecture, digital design, signal integrity, package, product engineering, and validation teams to ensure successful product execution.
• Mentor junior engineers and contribute to team-wide design methodologies and best practices.
• Drive technical reviews and provide leadership in solving complex design challenges.
Requirements
~1 min readBachelor's or master's degree in electrical engineering, Electronics Engineering, VLSI, Microelectronics, or a related discipline.
• 5 to 9 years of industry experience in analog/mixed-signal IC design.
• Strong expertise in CMOS analog circuit design fundamentals.
• Proven experience designing high-speed analog circuits in advanced technology nodes.
• Hands-on experience with one or more of the following: SerDes architectures, High-speed IO interfaces, PLL/DLL/CDR circuits, TX/RX analog front-end circuits, Clock distribution networks, Reference and bias circuits, LDOs and power management circuits.
• Deep understanding of circuit noise, mismatch, jitter, stability, and reliability considerations.
• Strong experience with Cadence Virtuoso, Spectre, and industry-standard analog verification flows.
• Expertise in: Corner analysis, Monte Carlo simulations, Statistical design methodologies, post-layout verification and extraction analysis, Strong debugging and analytical problem-solving skills.
• Experience with industry-standard high-speed interfaces such as: PCI Express (PCIe), DDR Memory Interfaces, USB, Ethernet, MIPI, DP, eDP, HDMI, UCIe.
• Experience in advanced process technologies such as FinFET and Gate-All- Around (GAA) nodes.
• Knowledge of signal integrity, channel modelling, and equalization techniques.
• Experience in silicon validation and lab characterization.
• Familiarity with reliability signoff, ESD verification, and EM/IR analysis.
• Scripting experience using Python, Perl, TCL, or SKILL for design automation and productivity enhancement.
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ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.Location & Eligibility
Listing Details
- Posted
- September 16, 2026
- First seen
- September 30, 2026
- Last seen
- September 30, 2026
Posting Health
- Days active
- 0
- Repost count
- 0
- Trust Level
- 24%
- Scored at
- September 30, 2026
Signal breakdown
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