CPU Circuit Design Engineer

You will join Intel's development center in Haifa/PTK, part of Intel's global organization responsible for designing next-generation CPU cores and SoCs using advanced process technologies.

As a CPU Circuit Design Engineer, you will work closely with senior design and development engineers on advanced CPU IP designs. You will contribute directly to multiple stages of the circuit design flow, including detailed circuit analysis, design implementation, and optimization at the transistor level, while applying industry best practices and proven methodologies.

The team focuses on delivering high-speed, best quality IP designs for CPUs that meet aggressive power, performance, and area targets. You will take ownership of defined design blocks, participate in technical decision-making, and be exposed to real-world design challenges using state-of-the-art EDA tools in a fast-paced, collaborative environment.

• Design, analyze, and debug CPU circuits at transistor level with increasing ownership

• Contribute to circuit-level implementation, optimization, and debugging across design stages using both manual design techniques and automation tools

• Perform power, performance, and area (PPA) analysis and drive design trade-offs for IP blocks

• Participate actively in design reviews, quality checks, and post-silicon debug support

• Collaborate with cross-functional teams including synthesis teams, Front End design (RTL), and layout

• Apply and help refine Intel circuit design methodologies and automation flows for IP development

• BSc or MSc in Electrical Engineering, Computer Engineering, or a related field.
• At least 2 years of experience in VLSI or circuit design. memory design or related CPU/SoC development is an advantage.
• Experience with industry-standard EDA tools for circuit design, simulation, and debugging
• Strong analytical and problem-solving skills, with the ability to work independently.
• Good communication skills and ability to collaborate effectively in a multidisciplinary team.
• Experience with transistor-level design, and power optimization techniques is an advantage.

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