~14d ago

IP RTL Senior Design Engineer

IndiaIndia·Bangaloresenior
EngineeringDesign Engineer
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Quick Summary

Key Responsibilities

Develop logic designs, register transfer level (RTL) coding, and simulations required for IP blocks, functional units, and subsystems.

Technical Tools
EngineeringDesign Engineer

Responsibilities

~1 min read
  • →Develop logic designs, register transfer level (RTL) coding, and simulations required for IP blocks, functional units, and subsystems.
  • →Define architecture and microarchitecture features for the IP block being designed.
  • →Apply strategies, tools, and methods to optimize RTL design for power, performance, area, and timing targets.
  • →Strong knowledge of AXI, AXI-Lite, APB, parity/ECC schemes, and transaction error handling.
  • →Experience with secure MMIO, access-control/firewall logic, or privilege-based filtering.
  • →Experience with RAS concepts such as fault containment, poison, interrupt generation, logging, and recovery-oriented design.
  • →Support SoC customers with seamless integration and verification of IP blocks.
  • →Telemetry and debug are both observability functions rather than primary Datapath functions.
  • →Drive compliance with quality assurance standards to enable smooth IP handoff within the SoC development process.

Requirements

~1 min read
  • Bachelor's degree in electrical engineering, Computer Engineering, or related field.
  • A minimum of 8 years of experience in logic design and RTL development.
  • Proficiency in hardware description languages such as Verilog, System Verilog.
  • Strong understanding of digital design principles, including timing analysis, power optimization, and area trade-offs.
  • Experience with industry-standard EDA tools for design and simulation (e.g., Synopsys, Cadence, Mentor Graphics).
  • Knowledge of IP block integration workflows within SoC designs.
  • Expertise in RAS/debug/security/telemetry.

  • Master's or PhD degree in Electrical Engineering, Computer Engineering, or related field.
  • 10+ years of professional experience encompassing complex IP logic design for high-performance applications.
  • Demonstrated expertise in architecture and microarchitecture definition.
  • Familiarity with advanced verification methodologies such as UVM or formal verification techniques.
  • Strong communication and collaboration skills, with a proven ability to work effectively in cross-functional teams.
  • A mindset for continuous learning and improvement, with an eagerness to tackle challenging, innovative design projects.
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

*

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

Location & Eligibility

Where is the job
Bangalore, India
On-site at the office
Who can apply
IN

About this job

Who can apply
India
Posted
14 days ago
Employer
has 941 open jobs on Jobera in 14 countries.

Listing Details

First seen
September 30, 2026
Last seen
October 15, 2026

Posting Health

Days active
14
Repost count
0
Trust Level
24%
Scored at
October 15, 2026

Signal breakdown

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IP RTL Senior Design Engineer