Quantum Qubit Design Engineer
Quick Summary
You must possess the below minimum qualifications to be initially considered for this position.
Requirements
~2 min readYou must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.
Minimum Qualifications:
• Bachelor's degree with 4 years of experience, Master's degree with 3 years of experience, or Ph.D. degree in Physics, Electrical Engineering, Cryogenic Engineering, Quantum Technologies, or Quantum Engineering or related Engineering field
• Must possess 1+ years experience with at least one of the following:
o Electromagnetic (EM) modeling and simulation tools and their application to signal integrity/crosstalk analysis for high-speed/high-density on-chip/on-package interconnect
o Standard cell design, design automation flow implementation (SKILL, VSR, MSOA or equivalent), and universal process file models and extraction
o Digital design tools and APR based routing design and ability to script and configure APR tools with languages such as TCL
o Designing and taping out designs on a mainstream foundry process PDK including running all industry standard validations such as DRC, ERC, LVS, PEX.
o Implementing PDK collateral and design flows to enable and maintain design environments
Preferred Qualifications:
• 1+ years of experience with:
o Electrical measurement experience with qubit, quantum devices, transistors, or integrated circuits
o Process-Integration experience with qubit or CMOS devices or interconnects
o Experience with dilution refrigerators or other cryogenic systems
o RFIC design or experience with cryogenic control of qubits
o Design of superconducting circuits and superconducting interconnects
o Programming, software, or driver development and scripting for task automation using languages such as Python
o Implementing Machine Learning or AI based digital design routing algorithms
o Working with EDA tool vendors to enable customized design solutions
What We Offer
~1 min readOur total rewards package goes above and beyond just a paycheck. Whether you're looking to build your career, improve your health, or protect your wealth, we offer generous benefits to help you achieve your goals. Go to Intel Benefits | Intel Careers for details of benefits available to you. Intel reserves the right to modify, change or discontinue benefit plans at any time in its sole discretion.
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $141,910.00-269,100.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
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ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.Location & Eligibility
Listing Details
- Posted
- September 22, 2026
- First seen
- September 29, 2026
- Last seen
- September 29, 2026
Posting Health
- Days active
- 0
- Repost count
- 0
- Trust Level
- 32%
- Scored at
- September 29, 2026
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