Senior SoC RTL Design Engineer

Mythic has developed a unified hardware and software platform featuring its unique Mythic Analog Compute Engine (Mythic ACE™) to deliver revolutionary power, cost, and performance that shatters digital barriers preventing AI innovation at the edge. Mythic's unique technology makes it much easier and more affordable to deploy powerful AI solutions, from the data center to the edge device. The company has raised over USD 125M in a recent funding round, and has offices in Palo Alto (CA, USA), Austin (TX, USA) and in Bangalore (Karnataka, India).

 

Mythic is a fast-paced startup looking for individuals that enjoy wide-reaching and flexible roles. The primary responsibility for this position is digital RTL design of Mythic's chips, but we are looking for individuals with strong computer architecture knowledge as well.

 

You will be the owner of all aspects of design and development for system-level blocks which form the SoC infrastructure. You will need to contribute, and ideally, have great ownership of, the architecture, microarchitecture, and RTL for a large high-performance system. Additionally, beyond defining what functionality these blocks provide, you will help drive methodologies to establish and enable first-pass success of these chips.

 

Beyond digital RTL design for our novel chip architecture, this role also presents a unique opportunity to get involved with and learn more about state-of-the-art deep neural networks (DNNs). You will also be collaborating with the system architecture, software, DFT, and analog design teams at Mythic.