~2d ago
New

ASIC TOP Floorplan Design Engineer

ChinaChina·Shanghaimid
EngineeringDesign Engineer
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Quick Summary

Key Responsibilities

Working with architects, design leads, physical design leads and package leads, you will develop, craft and optimize floorplans during early chip development.

Requirements Summary

Master’s degree in electrical engineering, Computer Science, or Computer Engineering and 1+ year equivalent work/learning experience. Experience in Verilog, System Verilog or similar HVL.

Technical Tools
EngineeringDesign Engineer

We are now looking for an ASIC Top Floorplan Design Engineer. NVIDIA is seeking a talented ASIC Floorplan Engineer to design and implement the world’s leading SoC's and GPU's. This position offers you a unique opportunity to craft and to influence the design and development of the next generation GPU and SoC, allowing you to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of exceptional people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. We are an AI-first team that strongly believes AI will transform the way we work and develop new chips.

Responsibilities

~1 min read
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    Working with architects, design leads, physical design leads and package leads, you will develop, craft and optimize floorplans during early chip development.

  • →

    Drive the area review process and collaborate with the ASIC design team to identify area, interconnect and floorplan improvement opportunities.

  • →

    Solve timing and routing congestion issues with physical and ASIC design teams by influencing early design and physical implementation decisions.

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    You will build tools and improve existing infrastructure using AI extensively to optimize chip area and speed of execution.

Requirements

~1 min read
  • Master’s degree in electrical engineering, Computer Science, or Computer Engineering and 1+ year equivalent work/learning experience.

  • Experience in Verilog, System Verilog or similar HVL.

  • Experience with CAD and physical design methodologies (flow and tool development), chip floorplan, power/clock distribution, packaging, P&R and timing closure.

  • Strong communication and interpersonal skills and ability & desire to work as a great teammate should be displayed in your interview.

  • Python, Perl and C/C++ programming language experience.

  • Experience using AI coding assistants like Cursor or Github copilot or Windchill

  • Experience in driving development of large-scale ASIC floorplan is a huge plus.

  • Experience building large projects from the ground up using AI tools.

  • Good command of spoken English

NVIDIA is widely considered to be one of the technology world’s most desirable employers. Our products are leading the way with groundbreaking developments in Artificial Intelligence, Autonomous Driving, High-Performance Computing and Visualization. We have some of the most forward-thinking and hardworking people in the world working for us. Are you creative and autonomous? Do you love the challenge of crafting the fastest and most power efficient chips in their class? If so, we want to hear from you.

Location & Eligibility

Where is the job
Shanghai, China
On-site at the office
Who can apply
CN

About this job

Who can apply
China
Posted
2 days ago
Employer
has 2,807 open jobs on Jobera in 24 countries.

Listing Details

First seen
October 18, 2026
Last seen
October 20, 2026

Posting Health

Days active
1
Repost count
0
Trust Level
51%
Scored at
October 20, 2026

Signal breakdown

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ASIC TOP Floorplan Design Engineer