1mo ago

Senior ASIC Design Engineer

2 Locationssenior
EngineeringDesign Engineer
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Quick Summary

Key Responsibilities

As a key member of the Design team, you will be responsible for the implementation of GPU sub-system modules. Make architectural trade-offs based on features, performance

Requirements Summary

Masters Degree (or equivalent experience) in Electrical Engineering or Computer Engineering. 8+ years of proven experience working

Technical Tools
EngineeringDesign Engineer

NVIDIA is seeking best-in-class ASIC Design Engineers to design and implement the world’s leading SoC's and GPU's. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of exceptional people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.

Responsibilities

~1 min read
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    As a key member of the Design team, you will be responsible for the implementation of GPU sub-system modules.

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    Make architectural trade-offs based on features, performance requirements and system limitations.

  • →

    You are expected to own micro-architecture, implement RTL, and deliver a fully verified, synthesis/timing clean design.

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    Support post-silicon validation activities.

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    Work with architects, other designers, pre- and post-silicon verification teams, synthesis, timing and back-end teams to accomplish your tasks.

Requirements

~1 min read
  • Masters Degree (or equivalent experience) in Electrical Engineering or Computer Engineering.

  • 8+ years of proven experience working on ASIC design and development.

  • Experience in micro-architecture and RTL development of complex designs in Verilog.

  • Exposure to Digital systems and VLSI design, Computer Architecture, Computer Arithmetic, CMOS transistors and circuits is required.

  • Understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug.

  • Prior experience with arbiters, scheduling, synchronization & bus protocols, interconnect networks, and/or caches is desirable.

  • Knowledge of PCI-Express (Gen 3 and above) or CXL protocol is very helpful; your firsthand design experience on it is a big plus.

  • Python, Perl and C/C++ programming language experience desirable.

  • Good debugging and analytical skills.

  • Strong interpersonal skills and ability & desire to work as a great teammate.

NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. Are you creative and autonomous? Do you love the challenge of crafting the fastest and most power efficient chips in their class? If so, we want to hear from you.

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5.

You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until October 9, 2026.

This posting is for an existing vacancy. 

NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

Location & Eligibility

Where is the job
Not specified
Location terms not specified
Who can apply
Same as job location

About this job

Posted
32 days ago
Employer
has 3,400 open jobs on Jobera in 29 countries.

Listing Details

Posted
October 6, 2026
First seen
October 18, 2026
Last seen
November 7, 2026

Posting Health

Days active
19
Repost count
0
Trust Level
13%
Scored at
November 7, 2026

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Senior ASIC Design Engineer