Senior ASIC Physical Design Engineer, Cache Coherent Interconnects

2 Locationssenior

EngineeringDesign Engineer

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Quick Summary

Key Responsibilities

As a member of our CPU team, you'll be responsible for synthesis and achieving timing, area, performance and power goals of the on-chip interconnect network and last-level caches.

Requirements Summary

Master’s Degree in Electrical Engineering, Computer Engineering or Computer Science or equivalent experience.

Technical Tools

EngineeringDesign Engineer

As a member of our CPU Cache Coherent Interconnects Design Team, you will be responsible for the physical design of CPU on-chip interconnect network and last-level caches, working on implementation, synthesis and timing closure while collaborating closely with the logic design team on micro-architecture definition and feasibility. This position offers you the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of extraordinary people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.

Responsibilities

~1 min read

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As a member of our CPU team, you'll be responsible for synthesis and achieving timing, area, performance and power goals of the on-chip interconnect network and last-level caches.
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Help evaluate the physical design for next-generation Nvidia coherent interconnects and system-level caches.

Requirements

~2 min read

Master’s Degree in Electrical Engineering, Computer Engineering or Computer Science or equivalent experience.
5+ years of experience in processor or other related high-performance semiconductor designs.
Physical design expertise in high-frequency design, including hands-on synthesis experience, timing analysis, floor-planning and in-depth knowledge of industry standard physical design tools is required.
Experience in interconnect/cache/core design is desirable.
Verilog expertise is preferred as is a deep understanding of ASIC design flow including RTL design and verification, DFT, and ECO.
Strong communication and interpersonal skills are required along with the ability to work in a dynamic, global team.

NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most brilliant and hardworking people in the world working for us. Are you creative and autonomous? Do you love the challenge of crafting the fastest and most power-efficient chips in their class? If so, we want to hear from you.

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 136,000 USD - 218,500 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4.

You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until August 14, 2026.

This posting is for an existing vacancy.

NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.