CMP Process Engineer

Role and Responsibilities

• Removal Rate (RR) Control: Conducting performance evaluations of various influence factors to ensure the thickness skew before and after CMP is consistent across the entire wafer.

• Condition Optimization: Determining the optimal process conditions to improve uniformity and resolve chronic issues, such as "center low RR profiles.

• Recipe Management: Developing and optimizing Recipe (RCP) parameters and improve flatness.

• Defect & uniformity Management: Managing and improving wafer uniformity and resolving defects such as scratches and particles.

• Consumable Life Cycle Management: Monitoring the usage cycles of consumables (pads, slurry) to ensure they do not exceed specifications, which could impact quality.

• Material Evaluation: Evaluating the performance of different slurries and polishing pads to optimize the CMP process.

Skills and Qualifications

• BS or MS in Chemical, Mechanical, Electrical, or Industrial Engineering, Physics, Chemistry, Material Science, or Computer Science.
• A minimum 5 years of related experience; Semiconductor Process Flows.
• Previous experience in a high-volume semiconductor manufacturing environment desired. Applicable manufacturing experience in other industries can be considered.
• Basic CMP Knowledge: Understanding of dielectric and metal CMP fundamentals, including slurry-pad-conditioning interactions and post-clean steps.
• Prefer to have some level of Equipment Familiarities: Hands-on experience with major industry CMP tools: AMAT/EBara and their end point systems
• Data & Statistics: Proficiency in Statistical Process Control (SPC), Fault Detection and Classification (FDC), and analysis software like JMP or Spotfire.
• Problem Solving: Ability to drive root-cause analysis using methodologies like FMEA, 8D, and first-principles physics approaches.
• Flexibility: As per business needs, sometimes it is required to work during off-hour times and/or with CWW shift schedule.

• Familiar with Metrology Tools: Experience with Ellipsometry, SEM, and AFM for thickness and roughness check.
• Experience on Defect Reduction: Experience identifying killer defects and improving wafer yield.
• Basic Idea of Fab Integration: Understanding of how CMP affects following steps (Etch/Photo) and overall yield.
• DOE: Ability to run structured Design of Experiments for process optimization.

Total Rewards
At Samsung Austin Semiconductor, base pay is just one part of our total compensation package. The base compensation for this role will depend on education, experience, skills, and location.

We offer a comprehensive benefits package, including:

• Medical, dental, and vision insurance
• Life insurance and 401(k) matching with immediate vesting
• Onsite café(s) and workout facilities
• Paid maternity and paternity leave
• Paid time off (PTO) + 2 personal holidays and 10 regular holidays
• Wellness incentives and MORE
   

Eligible full-time employees (salaried or hourly) may also receive MBO bonuses based on company, division, and individual performance.

All positions at Samsung Austin Semiconductor are full-time on-site.

Trade Secrets
 By submitting an application, you agree not to disclose to Samsung or induce or encourage Samsung to use any confidential or proprietary information (including trade secrets) belonging to a current or former employer or other entity.

* Please visit Samsung membership to see Privacy Policy, which defaults according to your location. You can change Country/Language at the bottom of the page. If you are European Economic Resident, please click here.

* Samsung Electronics America, Inc. and its subsidiaries are committed to Equal Employment Opportunity for all individuals regardless of race, color, religion, gender, age, national origin, marital status, sexual orientation, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.