Technical Lead - DFT

1. Defines SoC DFT architecture against test time, test cost, coverage, test power and pin budget.

2. Exposure to streaming scan networks (SSN) or tile-based hierarchical DFT for large SoCs.

3. Applies advanced fault models: cell-aware, path delay, small delay defect and IDDQ.

4. Owns SoC-wide MBIST and repair architecture, including shared-bus memory test.

5. Low-power DFT: power-domain aware scan and test-mode power management (UPF-aware DFT).

6. Owns DFT-mode STA sign-off criteria with the STA team.

7. Leads post-silicon work: ATE bring-up, failing-pattern diagnosis and yield diagnosis support.

8. Owns schedule, effort estimates, risk tracking and weekly status to the customer.

9. Leads DFT plan and sign-off reviews, and interviews candidates.

10. LBIST and in-system test for automotive (ISO 26262) is a plus.

DFT, SoC, tapeout

DFT architecture, streaming scan networks, tile-based hierarchical DFT