Technical Lead - DFT

1. Hierarchical DFT: core wrapping (IEEE 1500), pattern retargeting and top-level DFT integration.

2. Chooses scan compression configuration and chain balancing based on test time and pin budget.

3. Drives coverage closure through test-point insertion, ATPG constraint tuning and low-coverage debug.

4. MBIST with repair (BISR, eFuse) integration, and understanding of memory test algorithms.

5. Builds IJTAG (IEEE 1687) networks, TAP controller and boundary scan (IEEE 1149.1 / 1149.6).

6. Owns DFT-mode timing: shift, capture and at-speed constraints, OCC clock controllers, and closure with STA and PD teams.

7. Owns DFT gate-level simulation sign-off for all test modes.

8. Delivers ATE-ready patterns (STIL / WGL) and supports first-silicon bring-up on the tester.

9. Plans, estimates and tracks DFT tasks; mentors 2–3 engineers and reviews their work.

10. Builds automation for DFT flows and reports in Tcl or Python.

Hierarchical DFT, core wrapping, IEEE 1500

IJTAG networks, ATE bring-up, test-point insertion