Verification Technical Lead

1. Architects reusable, scalable UVM testbenches, including virtual sequencers, layered sequences, config objects, factory overrides and UVM RAL.

2. Leads verification planning: extracts features from the spec, defines the coverage model and sign-off criteria, and presents them in plan reviews.

3. Deep expertise in at least one complex protocol (PCIe, USB 3.x, Ethernet, DDR, CXL, AXI interconnect or MIPI), plus working knowledge of another.

4. Verifies at sub-system or SoC level: interconnect, clocks, resets and interrupts, and processor-driven C tests through DPI or embedded C.

5. Assertion-based verification. Exposure to formal verification (property or connectivity checks) is a plus.

6. Owns low-power (UPF) verification and gate-level simulation for their block or sub-system. Estimates effort, breaks work into tasks, and tracks coverage and bug-trend metrics with regular status reporting.

7. Mentors 2–3 engineers and reviews their testbench and test code.

8. Builds automation such as regression infrastructure and coverage or bug dashboards in Python.

UVM, testbench architecture, verification planning

formal verification, regression infrastructure, coverage dashboards