Senior Application Engineer - Semiconductor Test

Advantest America develops and supports advanced semiconductor test solutions for next-generation SoC, high-performance computing, RF, and mixed-signal products. We are building a high-caliber application engineering team for engineers who want ownership, customer impact, and hands-on access to leading-edge ATE, silicon, and lab infrastructure as demand for AI compute and inference accelerates.

This role places you near one of the most important semiconductor buildouts underway: AI compute and inference. You will help bring up, validate, and optimize advanced SoC devices for high-performance computing and large-scale AI infrastructure—working across silicon, software, ATE, and customer programs.

• We are seeking a hands-on Semiconductor Test Application Engineer in San Jose, CA. This role is ideal for an experienced ATE, validation, test development, or system-level debug engineer who wants to solve complex semiconductor test challenges with lab hardware, customer teams, and next-generation Advantest V93000 platforms.
• You will become a key technical owner for Advantest SmarTest 8 and V93000-based SoC test solutions, helping architect, debug, and optimize production-grade test programs for complex devices. Because the work includes hardware bring-up, lab execution, customer collaboration, and fast-moving ramps, the position is based on-site.

• →Test Program Development: Architect, write, debug, and optimize SoC test programs in modern ATE software environments, including Advantest SmarTest 8, for advanced AI compute, inference, and high-performance semiconductor devices.
• →Silicon Bring-Up and Validation: Support and help drive first-silicon bring-up on V93000 testers, debugging interactions between silicon, system behavior, test content, and the tester environment.
• →Pattern Workflow Engineering: Drive pattern translation, validation, and debug across DFT and tester workflows. Work with STIL, WGL, or comparable pattern sources; support tester bring-up; and collaborate with design and product engineering on emerging virtual test workflows using SmarTest 8 and V93000 environments.
• →Hardware Co-Design and Debug: Collaborate with PCB and hardware teams to specify, validate, and troubleshoot high-density Device Interface Boards (DIBs), including signal integrity, power delivery, and tester-to-device interfaces.
• →Test Time and Automation: Build automation in Python, Java, C++, or similar languages to analyze logs and STDF data, streamline debug, interface with test platforms, improve multi-site efficiency, and accelerate learning loops.

• →Education:S. or M.S. in Electrical Engineering, Computer Engineering, or a related technical discipline.
• →Location and Presence: Based in San Jose, CA, with regular on-site work at least three days per week across customer sites, lab environments, and/or the Advantest office.
• →ATE and Semiconductor Test Experience: Hands-on experience developing, debugging, or supporting test applications for manufacturing, characterization, validation, or production test. V93000 and SmarTest 8 experience is highly valued, but other ATE platforms or adjacent semiconductor test systems are also relevant.
• →SoC Test Foundations: Working knowledge of structural test, scan-based test strategies, memory BIST, logic BIST, high-speed digital I/O, or comparable SoC validation and production-test concepts.
• →Programming and Automation: Strong skills in Java, C/C++, Python, or similar languages, with the ability to build tools, automate workflows, parse test data, and debug hardware/software interactions.
• →Problem-Solving Mindset: Ability to move between software, hardware, silicon behavior, and customer constraints to diagnose issues and drive practical solutions.