ASIC Floorplan Design Engineer - New College Grad 2026

United States·Santa Claramid

EngineeringDesign Engineer

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Quick Summary

Key Responsibilities

Working with architects, design leads, physical design leads and package leads, you will develop and to craft and optimize floorplans during early chip development.

Requirements Summary

Masters Degree in Electrical Engineering, Computer Science, or Computer Engineering or equivalent experience.

Technical Tools

EngineeringDesign Engineer

We are now looking for a ASIC Floorplan Design Engineer - New College Graduate.

NVIDIA is seeking a talented ASIC Floorplan Engineer to design and implement the world’s leading SoC's and GPU's. This position offers you a unique opportunity to craft and to influence the design and development of the next generation GPU and SoC, allowing you to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of exceptional people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.

Responsibilities

~1 min read

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Working with architects, design leads, physical design leads and package leads, you will develop and to craft and optimize floorplans during early chip development.
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Drive the area review process and collaborate with the ASIC design team to identify area, interconnect and floorplan improvement opportunities
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Solve timing and routing congestion issues with physical and ASIC design teams by influencing early design and physical implementation decisions.
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You will build tools and improve existing infrastructure to optimize chip area and speed of execution.

Requirements

~1 min read

Masters Degree in Electrical Engineering, Computer Science, or Computer Engineering or equivalent experience.
A deep hardware engineering background with a concentration in VLSI and/or Computer Architecture.
Experience in Verilog, System Verilog or similar HVL
Experience with CAD and physical design methodologies (flow and tool development), chip floorplan, power/clock distribution, packaging, P&R and timing closure.
Strong communication and interpersonal skills and ability & desire to work as a great teammate should be displayed in your interview.
Python, Perl and C/C++ programming language experience

Experience in driving development of large scale ASIC floorplan is a huge plus.

NVIDIA is widely considered to be one of the technology world’s most desirable employers. Our products are leading the way with groundbreaking developments in Artificial Intelligence, Autonomous Driving, High-Performance Computing and Visualization. We have some of the most forward-thinking and hardworking people in the world working for us. Are you creative and autonomous? Do you love the challenge of crafting the fastest and most power efficient chips in their class? If so, we want to hear from you.

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 116,000 USD - 189,750 USD for Level 2, and 136,000 USD - 218,500 USD for Level 3.

You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until September 4, 2026.

This posting is for an existing vacancy.

NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.