Quick Summary
Overview
Senior Digital IC Designer Location: Milan,
Technical Tools
EngineeringDesign Engineer
Responsibilities
~1 min read- Develop RTL designs for complex digital blocks and subsystems using SystemVerilog/Verilog.
- Contribute to digital architecture definition together with senior designers and system architects.
- Analyze design trade-offs related to performance, power consumption, area, safety, and testability.
- Implement robust clocking, reset, and power management strategies.
- Support IP integration and subsystem-level development.
- Perform RTL verification activities, including simulation, lint, CDC, and synthesis checks.
- Collaborate closely with digital verification engineers to ensure specification coverage and design quality.
- Support timing closure and implementation activities.
- Participate in design reviews and contribute to sign-off readiness.
- Support silicon bring-up, debugging, characterization, and root-cause analysis.
- Work effectively within mixed-signal project teams including analog designers, verification engineers, system architects, and application engineers.
- Contribute to requirements definition and technical feasibility analysis.
- Support multiple development phases from concept through production release.
- Promote reuse of digital IPs and design methodologies.
- Contribute to the implementation of safety mechanisms in compliance with automotive standards.
- Support functional safety analysis and reviews.
- Follow established development processes and quality standards for automotive and industrial products.
- Provide technical support and guidance to less experienced engineers.
- Share knowledge, methodologies, and best practices within the team.
- Collaborate effectively across international R&D sites.
- Master's degree in Electrical Engineering, Electronics Engineering, or equivalent.
- Minimum 7 years of experience in digital IC design.
- Strong experience in RTL development using SystemVerilog/Verilog.
- Experience with synthesis, timing constraints, and digital implementation flows.
- Understanding of CDC, reset strategies, and low-power design concepts.
- Familiarity with DFT fundamentals and design-for-test methodologies.
- Experience working in mixed-signal IC development environments.
- Knowledge of digital verification methodologies and simulation-based verification.
- Experience with industry-standard EDA tools (Synopsys, Cadence, Siemens EDA).
- Fluent written and spoken English.
Requirements
~1 min read- Experience in automotive or industrial semiconductor products.
- Familiarity with automotive functional safety concepts (ISO 26262).
- Experience with electrification applications such as Battery Management Systems (BMS), High Voltage Gate Drivers, or Power Management ICs.
- Knowledge of digital signal processing techniques.
- Experience supporting first silicon bring-up and product qualification activities.
- Experience working within geographically distributed development teams.
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NXP is committed to equal pay for equal work and work of equal value and applies fair, consistent and transparent remuneration practices.
As of the date of this posting, the estimated gross annual base salary range for this position in Italy is between 50,600 € and 69,600 € annually. This range is intended as a guideline. Actual compensation may vary based on qualifications, experience, skills, and specific business or organizational needs. This position falls under the applicable National Collective Labour Agreement (Metalmeccanica Industria). Where relevant, the total compensation package may also include additional elements such as annual incentive opportunities and/or equity, along with a competitive benefits package.More information about NXP in Italy...
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#LI-6710Location & Eligibility
Where is the job
Milan, Italy
On-site at the office
Who can apply
IT
About this job
- Who can apply
- Italy
- Posted
- 17 days ago
Listing Details
- Posted
- October 5, 2026
- First seen
- October 18, 2026
- Last seen
- October 22, 2026
Posting Health
- Days active
- 3
- Repost count
- 0
- Trust Level
- 19%
- Scored at
- October 22, 2026
Signal breakdown
freshnesssource trustcontent trustemployer trust
External application
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