STD Cell QA Engineer

Role and Responsibilities

• Strong knowledge and hands-on experience in QA methodologies for standard cell libraries, including test plan development, regression testing, and post-layout verification
• 4 to 13 years of experience in Standard Cell Circuit design of high-performance flip flops, latches, multibit flip flops, voltage level shifters, power optimization cells, and clock cells.
• Strong knowledge and hands-on experience in developing environments and extracting post-layout netlists.
• Good understanding of CMOS device characteristics, design rules, latch-up, and electro migration.
• Proficiency in digital circuit simulation, design and optimization for better PPA.
• Hands-on experience in statistical/variation analysis.
• Contributing to the creation of cutting-edge semiconductor technologies that power a wide range of applications.
• Enhancing the performance and efficiency of standard cell circuits, impacting the overall quality of our products.
• Driving innovation in power optimization and clock cell design, leading to more energy-efficient solutions.

Skills and Qualifications

• B.Tech/B.E/M.Tech/M.E

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