RTL Design Engineer

Role and Responsibilities

• At least 6-10 years of experience in Low power RTL design, microarchitecture, synthesis, timing closure, power estimation. Should be proficient in Verilog/System Verilog.
• Should have experience in optimization of microarchitecture and RTL for area and power reduction. Experience with SoC integration, optimization of Arithmetic units, Floating point data path design is a plus. 
• Should have experience using ASIC design tools such as VCS, Verdi, Design Compiler, power estimation tools(such as Spyglass, PTPX). Knowledge of scripting languages (Shell, Perl, Python), C language is a plus.
• Experience with signing off RTL, synthesized netlist for Physical Design and eventually tape-out is desirable.
• Hands on experience with AXI, APB bus protocols is a must. Experience with PCIe, UCIe protocols is a plus.
• Prior domain experience in Artificial Intelligence and/or Near Memory acceleration is a plus. 
• Experience with hardware architecture exploration, performance modeling is desirable.
• *PPA - Power Performance, & Area analysis

Skills and Qualifications

• B.Tech/B.E/M.Tech/M.E

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