Principal Modem SOC Design Engineer - Terawave

Application close date:

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As a Principal Modem SOC Design Engineer on the ASIC Engineering SOC Team, you will be a technical design leader for the TeraWave satellite communication System on Chip (SOC). This individual contributor role carries technical leadership scope. You will lead RTL design for the modem SOC and its subsystems, define microarchitecture from communication system specifications, and drive integration across the modem PHY, Arm compute, debug, and IO infrastructure. As the technical interface among the system architecture, SOC architecture, software architecture, performance modeling, and FPGA prototyping teams, you will align design decisions from specification through production silicon.

• →Lead RTL design in Verilog or System Verilog for the modem SOC and its subsystems
• →Define microarchitecture based on satellite communication system specifications and performance requirements
• →Develop Arm compute subsystem logic, including AXI interconnect and SRAM controller integration
• →Integrate debug subsystem components using Arm CoreSight architecture and associated trace infrastructure
• →Drive subsystem and SOC-level integration, including clock, reset, and general-purpose IO (GPIO) subsystems
• →Serve as the technical interface to the system architecture, SOC architecture, and software architecture teams
• →Collaborate with performance modeling and FPGA prototyping teams on design decisions and validation

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field
• 12+ years of experience in digital ASIC or SOC RTL design
• Experience defining microarchitecture for modem or communication SOC blocks from system specifications
• Experience with Arm compute subsystem design, including AXI interconnect and SRAM controllers
• Experience with LPDDR4, LPDDR5, LPDDR6, or other high-speed memory interface subsystems
• Experience with high-speed Gigabit Ethernet interface subsystems
• Experience with SOC-level integration, including bus fabric, clock, and reset architecture
• Experience with debug subsystem design using Arm CoreSight components
• Experience with synthesis, timing constraint development, and timing closure support

• Master's degree in Electrical Engineering, Computer Engineering, or a related technical field
• Experience with RTL design in Verilog or System Verilog for modem datapath or PHY IP blocks
• Experience with signal processing hardware such as filters, FFTs, equalizers, or forward error correction (FEC)

Base Pay Range for:

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