Microarchitect and RTL Design Engineer
Quick Summary
Design and develop microarchitectures for a set of highly configurable IPs Microarchitecture and RTL coding ensuring optimal performance, power,
BS, MS in Electrical Engineering, Computer Engineering or Computer Science 8+ years and current hands-on experience in microarchitecture and RTL development Proficiency in Verilog,
Baya is a fast-moving Series B startup built by serial entrepreneurs with a vision to accelerate intelligent computing in the emerging chiplet era. We focus on software-driven, unified fabric solutions for single-die and multi-die systems. We design and license disruptive intellectual property for use in semiconductor chips, with software development platforms to simplify the design process and reduce the time to market for complex System-on-Chip (SoC) and multi-chiplet systems. This enables our partners to innovate and deliver compelling solutions for data center, infrastructure, AI, Automotive, and Edge IoT markets. We are looking for energetic and dedicated individuals share our passion for enabling innovation and excellence in the semiconductor industry that empowers game-changing products and services!
MICROARCHITECT AND RTL DESIGN ENGINEERS
Cambridge- or- Bristol, England, United Kingdom
About the role:
We are seeking seasoned Microarchitects and RTL Design Engineers with strong backgrounds in microarchitecture and RTL coding. The ideal candidates will play a key role in shaping our technology portfolio, bringing expertise and creativity to our solutions
Responsibilities:
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Design and develop microarchitectures for a set of highly configurable IPs
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Microarchitecture and RTL coding ensuring optimal performance, power, area
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Collaborate with software teams to define configuration requirements, verification collaterals, etc.
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Work with verification teams on assertions, test plans, debug, coverage, etc.
Qualifications and Preferred Skills:
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BS, MS in Electrical Engineering, Computer Engineering or Computer Science
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8+ years and current hands-on experience in microarchitecture and RTL development
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Proficiency in Verilog, System Verilog
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Familiarity with industry-standard EDA tools and methodologies
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Experience with large high-speed, pipelined, stateful designs, and low power designs
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In-depth understanding of on-chip interconnects and NoC's
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Experience designing IP blocks for caches, cache coherency, memory subsystems, interconnects and NoC's
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Familiarity with RAS designs, QoS in fabrics, PCIe/IO is a plus
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Experience with modern programming languages like Python is a plus
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Excellent problem-solving skills and attention to detail
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Strong communication and collaboration skills
What We Offer
~1 min readListing Details
- Posted
- March 24, 2026
- First seen
- March 26, 2026
- Last seen
- April 14, 2026
Posting Health
- Days active
- 19
- Repost count
- 0
- Trust Level
- 39%
- Scored at
- April 14, 2026
Signal breakdown
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