FPGA Design Engineer

• →Develop RTL for Xilinx (AMD) FPGA and/or Lattice CPLD designs
• →Selection of appropriate parts for designs weighing against numerous criteria such as cost, complexity, longevity, expandability, etc.
• →Design of hardware controls & knowledge in sequencing power, control and monitoring LSI and ASIC devices within compute, switch or storage board designs
• →Perform simulation, design, synthesis and timing validation in Verilog RTL
• →Creating IP for interface controllers, functionality as needed

• →Conduct reviews of your designs with the design and operations teams, and contribute to team schematic design reviews per HPE’s product design, development, and release processes

• →Generate programming models and work with firmware engineers on driver development
• →Work closely with board engineers for bring-up and testing of printed circuit assemblies
• →Lead or support debug of development and field issues. Track and document issue discovery, investigation plans/results, issue resolution, and issue closure in issue tracking data bases
• →Work with HPE partners and vendors to define requirements, support co-development or debug efforts
• →Work with FPGA vendors to understand roadmaps as well as new IP developments

• Bachelor's or Master's degree in Electrical Engineering.
• 4 or more years experience writing RTL for FPGAs for complex compute boards and/or ASIC designs
• Experience with BMC controllers, management interfaces for various CPU or GPU types, hardware management using I2C, SMBUS, JTAG, SPI, LPC, Wishbone, eSPI, PCIe, Ethernet, etc. protocols is desired
• Knowledge of server grade x86 and/or ARM and/or GPU processors is desired
• Experience with Xilinx Spartan 6, Spartan 7, Artix 7 families desired

• Ability to read and understand complex digital board schematics is required
• Ability to work independently and within design teams on multiple projects
• Ability to use lab equipment, scopes and analyzers, to debug complex problems
• Ability to work successfully with engineers across all geos to meet design requirements and schedules
• Excellent written and verbal communication skills
• Some travel may be required

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