Sr. Staff / Principal Physical Design Engineer

Join our Physical Design(SoC Integration)  team responsible for delivering high-performance SoC designs from RTL to GDS. As a Sr. Staff Physical Design Engineer, you will lead physical implementation efforts for advanced-node designs, driving critical blocks through synthesis, placement, CTS, routing, and signoff. You will work closely with front-end, DFT, power, and analog teams to optimize PPA (Power, Performance, Area) while ensuring silicon success. This role requires deep hands-on expertise across the full physical design flow as well as leadership to mentor junior engineers and define methodologies for the team.

• →Lead physical design implementation from synthesis through GDS for high-performance blocks or full-chip SoC designs in advanced process nodes (7nm, 5nm, 3nm)
• →Execute and optimize synthesis, placement, clock tree synthesis (CTS), and routing using industry-standard P&R tools (Synopsys ICC2/Fusion Compiler or Cadence Innovus)
• →Drive timing closure and signoff using PrimeTime (PT), including advanced analysis such as SI, AOCV/POCV, crosstalk, and ECO implementation
• →Perform RC extraction using StarRC or Quantus and ensure strong correlation between extraction and STA results
• →Own physical verification signoff with Mentor/Siemens Calibre, resolving DRC, LVS, ERC, and antenna violations in complex FinFET layouts
• →Conduct power integrity analysis using Ansys RedHawk(Redhawk-SC), including static/dynamic IR drop and EM analysis; implement power grid and decap optimizations
• →Develop and maintain physical design flows and automation scripts (Tcl, Perl, Python), mentor junior engineers, and collaborate with cross-functional teams to achieve tapeout schedules

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related field (Master's preferred)
• 8+ years of hands-on experience in ASIC physical design with proven tapeout success
• Expert-level proficiency in synthesis, placement, CTS, and routing using Synopsys or Cadence P&R tools
• Deep knowledge of static timing analysis (STA) and PrimeTime signoff, including multi-corner/multi-mode closure
• Demonstrated experience with physical verification using Calibre (DRC, LVS, ERC) and IR drop/EM analysis using RedHawk

• Experience at 5nm or 3nm process nodes with FinFET and multi-patterning design rules
• Familiarity with low-power design techniques including UPF, clock gating, multi-Vt, and voltage islands
• Strong programming skills in Tcl, Perl, and Python for flow automation and data analysis
• Knowledge of ECO implementation and clock reconstruction (CRPR, useful skew) methodologies
• Experience leading or mentoring a team of physical design engineers on complex SoC projects
• Exposure to memory-centric interfaces and systems such as SSD SoC, HBM, or HBF (High Bandwidth Flash) base die designs (a plus, not required)
• Familiarity with chiplet and die-to-die (D2D) interconnect technologies, including Universal Chiplet Interconnect Express (UCIe) or equivalent D2D PHY protocols (a plus, not required)