Technical Program Manager SOC & Digital Design

The Technical Program Manager will join our SoC team and oversee the development and integration of multiple chiplets supporting RISC-V CPU servers, machine learning processors, memory, and I/O functionality. This role requires experience across SoC architecture, design, verification, and integration from inception through tape-out, combined with strong program management skills to drive complex, cross-functional projects.

This role is hybrid, based out of Tokyo, Japan.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

• A technical program leader who can coordinate complex semiconductor development programs across internal teams and external contributors.
• A clear and confident communicator who can explain complex technical concepts to both technical and non-technical stakeholders.
• A structured problem-solver with strong judgment, decision-making skills, and the ability to proactively manage risks and dependencies.
• A collaborative leader who thrives in a fast-paced, dynamic environment and promotes teamwork and knowledge sharing.

• A bachelor’s or master’s degree in electrical engineering, computer engineering, or a related field, with 5+ years of experience in SoC chip design, technical program management, or engineering leadership.
• Strong understanding of the chip development lifecycle, including microarchitecture, design, verification, DFT, physical design, integration, and tape-out.
• Familiarity with industry standards and technologies such as AMBA, NoC, RISC-V, PCIe/CXL, and Ethernet.
• Demonstrated ability to develop and maintain program plans, track milestones and deliverables, lead program reviews, manage multiple projects, and drive cross-functional collaboration across design, verification, physical design, DFT, and software teams.

• →How complex chiplet-based SoC programs are planned and delivered from early architecture through tape-out.
• →How RISC-V CPU server and machine learning processor requirements influence integration, dependencies, and program execution.
• →How to coordinate internal engineering organizations, external contributors, and senior stakeholders on high-impact semiconductor programs.
• →How to identify program risks, implement corrective actions, and continuously improve execution across the SoC development lifecycle.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.