Lead STA Engineer
Administration & Office SupportStaff Design
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Quick Summary
Key Responsibilities
Create, validate, and maintain Synopsys Design Constraints (SDC) for block and full-chip levels, covering false paths, multicycle paths, and test modes.
Requirements Summary
Master's degree or Bachelor's degree in Electronics/ Electrical Engineering, Computer Engineering, or a related field.
Technical Tools
Administration & Office SupportStaff Design
Requirements
~1 min read- Master's degree or Bachelor's degree in Electronics/ Electrical Engineering, Computer Engineering, or a related field.
- 7+ years of hands-on experience in static timing analysis for complex ASIC/SoC designs.
- Experience of Multi mode timing constraint development, execution, and final timing signoff for advanced technology nodes
- Proven experience leading STA efforts for multiple successful tape-outs.
- Expertise in industry-standard STA tools (e.g., Synopsys PrimeTime, Cadence Tempus).
- Strong understanding of digital design fundamentals, clocking architectures, and low-power techniques
- In-depth knowledge of timing constraints (SDC) and their application.
- Proficiency in scripting languages such as Perl, Python, or TCL.
- Strong communication and interpersonal skills, with the ability to collaborate effectively in a global team environment.
- Work closely with Architects,Front End,DFT and the PD team to understand design,clocking,timing ,Requirements and lead the writing constraints and closing timing activities
Responsibilities
~1 min read- →Constraint Development: Create, validate, and maintain Synopsys Design Constraints (SDC) for block and full-chip levels, covering false paths, multicycle paths, and test modes.
- →Timing Signoff: Perform exhaustive timing analysis across multiple corners and modes (MCMM), adhering to process, voltage, and temperature (PVT) variations.
- →Violation Debugging: Debug and resolve setup, hold, transition, and path-based violations (PBA).
- →Optimization & ECO: Drive timing closure by generating and evaluating timing Engineering Change Orders (ECOs).
- →Cross-functional Collaboration: Partner with RTL, physical design, and DFT teams to ensure robust timing integration and refine timing models.
- →Tool & Flow Automation: Develop and support implementation flows using industry-standard Electronic Design Automation (EDA) tools and improve script-based automation.
- →Drive a small team of STA engineers.
- →Should be able to do IP level synthesis.
Location & Eligibility
Where is the job
Bangalore, India
On-site at the office
Who can apply
IN
About this job
- Who can apply
- India
- Posted
- 30 days ago
Listing Details
- Posted
- September 25, 2026
- First seen
- October 18, 2026
- Last seen
- October 25, 2026
Posting Health
- Days active
- 6
- Repost count
- 0
- Trust Level
- 14%
- Scored at
- October 25, 2026
Signal breakdown
freshnesssource trustcontent trustemployer trust
External application
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