2d ago
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Senior STA Engineer

IsraelIsrael·Tel Avivsenior
Administration & Office SupportStaff Design
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Quick Summary

Key Responsibilities

Drive static timing analysis and timing closure for block and/or full-chip designs. Develop, review, and debug timing constraints, scenarios, and signoff checks. Analyze setup, hold, noise,

Requirements Summary

B.Sc. or M.Sc. in Electrical Engineering, Computer Engineering, or equivalent experience. 5+ years of experience in ASIC or SoC physical design, timing analysis, or implementation.

Technical Tools
Administration & Office SupportStaff Design

NVIDIA is seeking a Physical Design and Timing Engineer to join our silicon implementation team. This role focuses on timing analysis, timing closure, and signoff quality across complex ASIC and SoC designs. You will work closely with physical design, front-end design, methodology, and CAD teams to drive robust implementation at advanced process nodes. This is a strong fit for an engineer who enjoys deep analysis, problem solving, and improving quality at block and full-chip levels.


Responsibilities

~1 min read
  • →Drive static timing analysis and timing closure for block and/or full-chip designs.
  • →Develop, review, and debug timing constraints, scenarios, and signoff checks.
  • →Analyze setup, hold, noise, and variation-related timing issues and drive closure with cross-functional teams.
  • →Partner with physical design engineers on floorplan, CTS, route, ECO, and convergence activities.
  • →Review reports, identify root causes of violations, and recommend high-quality fixes with minimal design impact.
  • →Improve timing methodology, automation, and debug efficiency using Tcl, Perl, and/or Python.

Requirements

~1 min read
  • B.Sc. or M.Sc. in Electrical Engineering, Computer Engineering, or equivalent experience.
  • 5+ years of experience in ASIC or SoC physical design, timing analysis, or implementation.
  • Strong understanding of static timing analysis fundamentals, timing constraints, and timing closure.
  • Hands-on experience with industry-standard EDA tools such as PrimeTime, ICC2, Innovus, Tempus, or equivalent.
  • Experience debugging setup/hold violations, clocking issues, and ECO impacts.
  • Solid scripting skills in Tcl plus familiarity with Perl or Python.
  • Good communication skills and ability to work across design, CAD, and verification teams.

  • Experience with advanced-node implementation and signoff.
  • Knowledge of MMMC flows, SI, OCV/AOCV/POCV, and power-aware timing analysis.
  • Experience improving timing methodology or developing reusable automation.

We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. We will ensure that individuals with disabilities are provided a reasonable accommodation to participate in the job application or interview process, perform essential job functions, and receive other benefits and privileges of employment. Please contact us to request accommodation.

Location & Eligibility

Where is the job
Tel Aviv, Israel
On-site at the office
Who can apply
IL

About this job

Who can apply
Israel
Posted
2 days ago
Employer
has 3,297 open jobs on Jobera in 29 countries.

Listing Details

Posted
November 2, 2026
First seen
November 2, 2026
Last seen
November 4, 2026

Posting Health

Days active
1
Repost count
0
Trust Level
51%
Scored at
November 4, 2026

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Senior STA Engineer